The CS4350 PLL DAC Simplifies System Design
Posted Sep 13, 2013 at 10:00 am
Typical Digital to Analog Converters (DACs) require a high-speed Master Clock to clock their digital filters and modulators, as well as some portions of their discrete time analog circuitry. This Master Clock (or system clock) is typically required to be synchronous to the left-right (frame or word) clock (LRCK) in order to maintain sample alignment in the digital filters, state machines, modulator and discrete time analog sections. Figure 1 below shows an example of a typical DAC clocked by an external Master Clock. The clock is applied to the MCLK pin and then distributed to any internal logic that requires it.
Figure 1 The CS4350 PLL DAC Simplifies System Design image1
As an alternative, PLL DACs are designed to derive their internal synchronous Master Clock from some other external source. This source could be any clock, but in practice it is commonly a video clock (27 MHz) or one of the slowerSCLK or LRCK signals which are mandatory for typical PCM audio interfaces (See AN282 “The 2-Channel Serial Audio Interface: A Tutorial”). In practice, the CS4350 PLL DAC generates its Master Clock from the input left right clock. Figure 2 shows the CS4350 PLL DAC architecture; from the input LRCK signal, the internal PLL derives the Master Clock signal that is used to drive the internal system timing.
Figure 2 The CS4350 PLL DAC Simplifies System Design image2
The internal Master Clock generation of a PLL DAC yields inherent benefits that simplify the design of audio systems. The CS4350’s unique implementation of the feature takes the concept a step further to provide an even greater degree of design simplicity, flexibility, and performance.
